why use CROSS_COMPILE variable when we compile C code Makefile?

So I want to cross compile my source code using arm-linux-androideabi-gcc so for this, I write simple C code into files like main.c and main.h now make "Makefile" and write code into this file like,

     CC=arm-linux-androideabi-gcc
     SRC=adc.c
     INC=./
     OBJ=si7006

     all:
             $(CC) $(SRC) -I$(INC) -o $(OBJ)

     clean:
             rm -rf $(OBJ)

now I have 2 questions (1) What is the use of -I$(INC) without it "make" is working file (2) After writing Makefile I use "make" command to compile it so when I used only "make" it show errors like,

arm-linux-androideabi-gcc adc.c -I./ -o adc make:

arm-linux-androideabi-gcc: Command not found make: *** [all] Error 127

if I add CROSS_COMPILE variable at make line (Ex:- make CROSS_COMPILE=arm-linux-androideabi- ) it working file why ??

-> so the solution is export CC="arm-linux-androideabi-gcc" and then use "make" command only for compile the Makefile and the output is like, arm-linux-androideabi-gcc adc.c -I./ -o adc