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Why does this MakeFile rule have two colons?

$
0
0
$(EXEX) : main% : $(OBJS) pp%.o
    gcc $(FLAGS) $^ -o $@

I am just trying to understand the above. As I understand it, everything in EXEX are targets which will be built using the following pattern.

main, OBJS and pp.o are prerequisites for things in EXEX. The second line will compile $^(meaning all the prereqs) using gcc with all the flags in FLAGS as object files in order to build $@ which is the contents of EXEX. There need to be rules to build all those -o's.

My question is why are there two colons? Is this two rules? Does main% mean = main with any file ending? Why do we need the % in pp%.o, what does it mean in this case? It seems to have many many purposes.


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