//makefile.conf
.SUFFIXES : .c .occ = gccCFLAG = -cOFLAG = -oO2FLAG = -O2WPIFLAG = -lwringPiRM = rm -rfTARGET_SRCS = main.cTARGET_OBJS = $(TARGET_SRCS:$.c=$.o)TARGET_NAMES = $(TARGET_SRCS:$.c=$)BINARY_NAME = LED_TEST// makefile
include makefile.conf$(TARGET_OBJS) : $(TARGET_SRCS) $(CC) $(O2FLAG) $(CFLAG) $(OFLAG) $^Hi, I'm trying to figure out how gnu make works and how to use it. Yet, I'm noob as hell.
I'm trying to use make on my assignment(not mandatory, just my passion.. maybe being arrogant i guess) for running simple code which lights up LED by using wiringpi.
actually there's only one main.c and what I want to make is the makefile that runs
gcc -O2 -c -o main.o main.c
gcc -o main main.o -lwiringPi
Since my last code didn't worked, (constantly getting circular main.c <- main.c dependency dropped error)
I tried to make a code that only runs
gcc -O2 -c -o main.o main.c
but i still get circular main.c error and I don't know what the hell does that means.
I tried to look up gnu make manuals but I thought through that, It will take my life to understand.
So I'm trying to see the codes and make one with what I saw..
I think I understand the concept of makefile.conf but still don't understand the function of .SUFFIXES.
I understood it as noticing make that I'll make a rule with .c and .o, codes after that in makefile.conf defines the variables those will be used in makefile.
What would be the correrct code?? I've been struggling with this for more than 4 hours. When actual 'assignment' took only five minute including adding comments.
Please help me.
Also, It would be grateful if you recommend me a proper book for make. (I guess easy one would be better because English is my second language).
Thanks..