Multi target makefile with subfolders

My project has the following structure:

\---Project+   Makefile    |+---source    |   +---target1    |   |       t1_lib.c    |   |       t1_main.c    |   |           |   +---target2    |   |       t2_lib.c    |   |       t2_main.c    |   |           |   \---common    |           common_lib.c    |+---headers+---target1        |       t1_lib.h        |       +---target2        |       t2_lib.h        |               \---common                common_lib.h

I am trying to write a makefile which allows me to run 'make target1' or 'make target2' and compile target1 source code with common source code or compile target2 source code with common source code respectively.

In my project, target1 is call 'ue' and target2 is call 'enb'.This is what I have in my current makefile:

# Author: j0lama# COMPILERCC = gcc#FLAGSCFLAGS = -c -Wall -ansi -g -std=c99 -D_DEBUG#LIB FLAGSLIBFLAGS = -lgc -rdynamic -lcrypto -lpthread#LINK FLAGSLINKFLAGS = -lsctp# PATHSUE_SOURCE_DIRECTORY = source/ue/UE_INCLUDE_DIRECTORY = headers/ue/ENB_SOURCE_DIRECTORY = source/enb/ENB_INCLUDE_DIRECTORY = headers/enb/COMMON_SRC_DIRECTORY = source/common/COMMON_HDR_DIRECTORY = headers/common/OBJECT_DIRECTORY = objects/BUILD_DIRECTORY = build/COMMON_CFILES= $(wildcard $(COMMON_SRC_DIRECTORY)*.c)COMMON_OBJECTS= $(patsubst $(COMMON_SRC_DIRECTORY)%.c, $(OBJECT_DIRECTORY)%.o, $(COMMON_CFILES))CFILES = $(COMMON_CFILES)OBJECTS = $(COMMON_OBJECTS)all: clean ue enbue: setup_ue $(OBJECT_DIRECTORY) $(TARGET) ue_emulatorenb: setup_enb $(OBJECT_DIRECTORY) $(TARGET) enb_emulatorsetup_ue:    $(eval CFILES += $(wildcard $(UE_SOURCE_DIRECTORY)*.c))    $(eval OBJECTS += $(patsubst $(UE_SOURCE_DIRECTORY)%.c, $(OBJECT_DIRECTORY)%.o, $(wildcard $(UE_SOURCE_DIRECTORY)*.c)))    $(eval INCLUDE_DIRECTORY = $(UE_INCLUDE_DIRECTORY))setup_enb:    $(eval CFILES += $(wildcard $(ENB_SOURCE_DIRECTORY)*.c))    $(eval OBJECTS += $(patsubst $(ENB_SOURCE_DIRECTORY)%.c, $(OBJECT_DIRECTORY)%.o, $(wildcard $(ENB_SOURCE_DIRECTORY)*.c)))    $(eval INCLUDE_DIRECTORY = $(ENB_INCLUDE_DIRECTORY))$(OBJECT_DIRECTORY):    @mkdir $(OBJECT_DIRECTORY)    @echo "Building objects directory..."ue_emulator: $(OBJECTS)    @echo "Building $@..."    @$(CC) $(OBJECTS) $(LIBFLAGS) $(LINKFLAGS) -o $@enb_emulator: $(OBJECTS)    @echo "Building $@..."    @$(CC) $(OBJECTS) $(LIBFLAGS) $(LINKFLAGS) -o $@$(OBJECT_DIRECTORY)%.o: $(SOURCE_DIRECTORY)%.c $(COMMON_SRC_DIRECTORY)%.c    @echo "Building $@..."    @$(CC) -I $(COMMON_HDR_DIRECTORY) -I $(INCLUDE_DIRECTORY) $(CFLAGS) $(LIBFLAGS) $< -o $@.PHONY: cleanclean:    @echo "Removing objects files"    @rm -rf $(OBJECT_DIRECTORY) $(TARGET)

Somehow this makefile does not compile any file.